Simulation Of Optimized Low Power Cmos Digital Processor Design Using 32nm Technology
Keywords:
Low Power, 4-bit Nano-Processor, 90nm, 45nm, 32nm, Power consumption, Power-Gating, Clock-Gating, ANNAbstract
In this work a CMOS based 4-bit processor is implemented with and without ANN. The foundry technologies used are 90nm, 45nm, 32nm. The simulations are performed and the power results along with no of MOSFETS are mentioned. The proposed work obtained promising results when compared with previous works. Nano processors utilize advanced fabrication techniques to create transistors and other components with nanoscale dimensions. These transistors can operate in conditions where classical physics laws may no longer directly apply and quantum effects can become significant. This introduces new challenges and opportunities for computing. In this research work, implementation of a 4-bit nano-processor utilizing Tanner Electronic Design Automation tool is proposed. The processor is developed using a cutting-edge 90nm, 45nm, 32nm technology files, focusing on achieving compactness, low power consumption, and efficient performance. The design process encompasses various stages, including schematic capture, simulation, and power analysis. The proposed Nano processor begins with a 4bit ALU that incorporates all fundamental and universal gates, an efficient and high-speed adder, multiplier, and multiplexer. The major subcomponents that can be changed are the Carry Save Adder and the multiplier. Power consumption and area reduction is optimised. The proposed Nano processor’s second component is a 4-bit 6T SRAM, encoder and decoder, and an Artificial Neural Network. All of these subcomponents are created at the transistor level. Nano processors refer to a class of extremely small-scale integrated circuits designed to perform computation at the nanometre scale. The simulation results show for 90nm, power dissipation of 0.7009451 µW. For 45nm, power dissipation of 0.05211081µW. For 32nm, power dissipation of 0.0278810µW. With Power gating technique the obtained power is 0.05344917µw when compared with existing result. With Clock gating technique 6.044895 µW.
